Ao Ren
Professor
Email: ren.ao@wnmb900.com
Ao Ren obtained his Ph.D. degree from the Department of Electrical and Computer Engineering, Northeastern University, MA, USA. He served as an Assistant Professor in the Department of Electrical and Computer Engineering, Clemson University, SC, USA. He is a Professor at the College of Computer Science, Chongqing University, China. His research centers around energy-efficient deep learning systems for edge devices, which include deep learning compression algorithms, the deep learning compiler, and the deep learning accelerator architecture for both FPGAs and ASICs. His other research interests include multimodal learning, few-shot learning, and approximate computing. His work has appeared in some of the top venues in computer architecture and artificial intelligence, such as ASPLOS, ISCA, AAAI, ISSCC, and ICCAD. He has served as the TPC members of ASAP, ICMLA, and ICCAD.
Selected Publication (* Equal Contribution)
Conference Papers
1. [IJCNN'21] Li Li, Moming Duan, Duo Liu, Yu Zhang, Ao Ren, Xianzhang Chen, Yujuan Tan and Chengliang Wang, “FedSAE: A Novel Self-Adaptive Federated Learning Framework in Heterogeneous Systems,” in Proc. of the International Joint Conference on Neural Networks (IJCNN), 2021. (CCF C)
2. [IJCNN'21] Yu Zhang, Moming Duan, Duo Liu, Li Li, Ao Ren, Xianzhang Chen, Yujuan Tan and Chengliang Wang, “FedSAE: A Novel Self-Adaptive Federated Learning Framework in Heterogeneous Systems,” in Proc. of the International Joint Conference on Neural Networks (IJCNN), 2021. (CCF C)
3. [AAAI'20] A. Ren, T. Zhang, Y. Wang, S. Lin, P. Dong, Y.K. Chen, Y. Xie, and Y. Wang, “DARB: A Density-Adaptive Regular-Block Pruning for Deep Neural Networks,” in Proc. of the 34th AAAI Conference on Artificial Intelligence (AAAI), 2020. (CCF A，Acceptance Rate：20.8%)
4. [ASPLOS'19] A. Ren, T. Zhang, S. Ye, W. Xu, X. Qian, X. Lin, and Y. Wang, “ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Methods of Multipliers,” in Proc. of the 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2019. (CCF A，Acceptance Rate：21.1%)
5. [ISCA'19] R. Cai, A. Ren, O. Chen, N. Liu, C. Ding, X. Qian, J. Han, W. Luo, N. Yoshikawa, and Y. Wang, “A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology,” in Proc. of the 46th International Symposium on Computer Architecture (ISCA), 2019. (CCF A，Acceptance Rate：16.9%)
6. [ISSCC'19] J. Yue, R. Liu, W. Sun, Z. Yuan, Z. Wang, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang, X. Li, H. Yang, and Y. Liu, “7.5 A 65nm 0.39-to-140.3 TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1× Higher TOPS/mm2 and 6T HBST-TRAM-Based 2D Data-Reuse Architecture,” in Proc. of IEEE International Solid-State Circuits Conference (ISSCC), 2019. (CCF A)
7. [ICCD'19] R. Cai, O. Chen, A. Ren, N. Liu, N. Yoshikawa, and Y. Wang, “A Buffer and Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits,” in Proc. of the 37th IEEE International Conference on Computer Design (ICCD), 2019. (CCF B)
8. [GLVLSI'19] R. Cai, O. Chen, A. Ren, N. Liu, C. Ding, N. Yoshikawa, and Y. Wang, “A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits,” in Proc. of the 29th ACM Great Lakes Symposium on VLSI (GLVLSI), 2019. (CCF C)
9. [ISVLSI'19] R. Cai, X. Ma, O. Chen, A. Ren, N. Liu, N. Yoshikawa, and Y. Wang, “IDE Development, Logic Synthesis and Buffer/Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits,” in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019. (CCF C)
10. [ASPLOS'18,] R. Cai, A. Ren*, N. Liu, C. Ding, L. Wang, X., M. Pedram, and Y. Wang, “VIBNN: Hardware acceleration of Bayesian neural networks,” in Proc. of the 23th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2018. (CCF A，Acceptance Rate：17.6%)
11. [GLVLSI'18] C. Ding, A. Ren*, G. Yuan, X. Ma, J. Li, N. Liu, B. Yuan, and Y. Wang, “Structured weight matrices-based hardware accelerators in deep neural networks: FPGAs and ASICs,” in Proc. of the 28th ACM Great Lakes Symposium on VLSI (GLVLSI), 2018. (CCF C)
12. [ISVLSI'18] Z. Li, J. Li, A. Ren, C. Ding, J. Draper, Q. Qiu, B. Yuan, and Y. Wang, “Towards budget-driven hardware optimization for deep convolutional neural networks using stochastic computing,” in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018. (CCF C)
13. [ISQED'18] X. Ma, Y. Zhang, G. Yuan, A. Ren, Z. Li, J. Han, J. Hu, and Y. Wang, “An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing,” in Proc. of 19th International Symposium on Quality Electronic Design (ISQED), 2018. Best paper nomination
14. [ASPLOS'17] A. Ren, J. Li, Z. Li, C. Ding, X. Qian, Q. Qiu, B. Yuan, and Y. Wang, “SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing,” in Proc. of the 22th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2017. (CCF A，Acceptance Rate：17.4%)
15. [ICCAD'17] H. Li, T. Wei, A. Ren, Q. Zhu, and Y. Wang, “Deep reinforcement learning: Frame-work, applications, and embedded implementations,” in Proc. of the 36th International Conference on Computer-Aided Design (ICCAD), 2017. (CCF B)
16. [ICCD'17] R. Cai, A. Ren, L. Wang, M. Pedram, and Y. Wang, “Hardware acceleration of Bayesian neural networks using RAM based linear feedback gaussian random number generators,” in Proc. of the 35th IEEE International Conference on Computer Design (ICCD), 2017. (CCF B)
17. [MWSCAS'17] G. Yuan, C. Ding, R. Cai, X. Ma, Z. Zhao, A. Ren, B. Yuan, and Y. Wang, “Memristor crossbar-based ultra-efficient next-generation baseband processors,” in Proc. of the 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2017.
18. [IJCNN'17] J. Li, Z. Yuan, Z. Li, C. Ding, A. Ren, Q. Qiu, J. Draper, and Y. Wang, “Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks,” in Proc. of the International Joint Conference on Neural Networks (IJCNN), 2017. (CCF C)
19. [GLVLSI'17] Z. Yuan, J. Li, Z. Li, C. Ding, A. Ren, B. Yuan, Q. Qiu, J. Draper, and Y. Wang, “Softmax regression design for stochastic computing based deep convolutional neural networks,” in Proc. of the 27th ACM Great Lakes Symposium on VLSI (GLVLSI), 2017. (CCF C)
20. [DATE'17] Z. Li, A. Ren, J. Li, Q. Qiu, B. Yuan, J. Draper, and Y. Wang, “Structural design optimization for deep convolutional neural networks using stochastic computing,” in Proc. of the Conference on Design, Automation and Test in Europe (DATE), 2017. (CCF B)
21. [ICASSP'17] S. Liu, A. Ren, Y. Wang, P. K. Varshney, “Ultra-fast robust compressive sensing based on memristor crossbars,” in Proc. of 42nd IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2017. Best Paper Award, Best Student Presentation Award (Top 3 in more than 2,000 submissions) (CCF B)
22. [ASP-DAC'17] A. Ren, S. Liu, R. Cai, W. Wen, P. K. Varshney, and Y. Wang, “Algorithm-hardware co-optimization of the memristor-based framework for solving SOCP and homogeneous QCQP problems,” in Proc. of 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017.(CCF C)
23. [ASP-DAC'17] J. Li, A. Ren, Z. Li, C. Ding, B. Yuan, Q. Qiu, and Y. Wang, “Towards acceleration of deep convolutional neural networks using stochastic computing,” in Proc. of 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017. (CCF C)
24. [ICRC'16] A. Ren, Z. Li, B. Yuan, Q. Qiu, and Y. Wang, “Designing reconfigurable large-scale deep learning systems using stochastic computing,” in Proc. of IEEE International Conference on Rebooting Computing (ICRC), 2016.
25. [ICCD'16] Zhe Li, A. Ren*, J. Li, Q. Qiu, Y. Wang, and B. Yuan, “DSCNN: Hardware-oriented optimization for Stochastic Computing based Deep Convolutional Neural Networks,” in Proc. of the 34th IEEE International Conference on Computer Design (ICCD), 2016. (CCF B)
26. [SOCC'16] A. Ren, B. Yuan, and Y. Wang, “Design of high-speed low-power polar BP decoder using emerging technologies,” in Proc. of the 29th IEEE International System-on-Chip Conference (SOCC), 2016.
27. [ISVLSI'16] R. Cai, A. Ren, Y. Wang, and B. Yuan, “Memristor-based discrete Fourier transform for improving performance and energy efficiency,” in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
Journal Papers
28. [JSSC'20] J. Yue, R. Liu, W. Sun, Z. Yuan, Z. Wang, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang, X. Li, H. Yang, and Y. Liu, “STICKER-T: An Energy Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration,” in the IEEE Journal of Solid State Circuits (JSSC), 2020. (SJR Q1)
29. [2D Mater. '19] Y. Qiang, A. Ren*, X. Zhang, P. Patel, X.n Han, K. Seo, Z. Shi, Y. Wang, and H. Fang, “Design of Atomically-Thin-Body Field-Effect Sensors and Pattern Recognition Neural Networks for Ultra-Sensitive and Intelligent Trace Explosive Detection,” in 2D Materials, 2019. (SJR Q1)
30. [INTEGRATION'19] J. Li, Z. Yuan, Z. Li, A. Ren, C. Ding, J. Draper, S. Nazarian, Q. Qiu, B. Yuan, and Y. Wang, “Normalization and dropout for stochastic computing-based deep convolutional neural networks,” in Integration, the VLSI Journal, 2017. (SJR Q1)
31. [TCAD'18] Z. Li, J. Li, A. Ren, R. Cai, C. Ding, X. Qian, J. Draper, B. Yuan, J. Tang, Q. Qiu, and Y. Wang, “HEIF: Highly Efficient Stochastic Computing based Inference Framework for Deep Neural Networks,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.(CCF A, SJR Q2)
32. [Nano Commun. Netw. '18] R. Cai, A. Ren, S. Soundarajan, and Y. Wang, “A low-computation-complexity, energy-efficient, and high-performance linear program solver based on primal–dual interior point method using memristor crossbars,” in Nano Communication Networks, 2018. (SJR Q2)
Patent Applications
1. A. Ren, Y. Wang, T. Zhang, Y. Xie, “Structured Pruning for Machine Learning Model,” US Patent
2. A. Ren, T. Zhang, Y. Wang, Y. Xie, “Method and System for Processing a Neural Network,” US Patent
3. F. Sun, A. Ren, “Artificial Neural Network with Sparse Weights,” US Patent
